The development of a semiconductor device in which p-channel and n-channel thin film transistors (TFTs) are formed on one and the same substrate and electronic equipment including such a semiconductor device is promoted.
For example, in an active matrix liquid crystal display device or an organic EL display device, a technique in which a driving circuit is integrally formed on an active matrix substrate is suggested. For the driving circuit, a CMOS (Complementary Metal Oxide Semiconductor) including a p-channel TFT (hereinafter abbreviated as “a p-type TFT”) and an n-channel TFT (hereinafter abbreviated as “an n-type TFT” is employed. In the case where the CMOS is employed, in order to prevent leakage current from occurring, it is necessary to adjust the driving voltage for each TFT in such a manner that two types of TFTs which constitute the CMOS are both in the OFF state when a gate voltage is not applied. From the point of view of the reduction in electric power consumption, it is desired that the driving voltage of TFT be lowered.
On the other hand, in an active matrix liquid crystal display device or an organic EL display device, a technique in which a memory circuit is provided for each pixel on the active matrix substrate is suggested (Patent Document No. 1 or the like). With such a configuration, image data of each pixel can be stored in the memory circuit provided in the pixel (hereinafter, referred to as “an image memory”), so that a still image can be displayed with low power consumption without continuously supplying image data from the external.
As for the image memory, it is suggested to employ a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). The SRAM can operate at higher speed than the DRAM, and does not require refresh operation unlike the DRAM, so that it is possible to further suppress the power consumption. The SRAM has a flip-flop circuit utilizing a plurality of TFTs including p-type and n-type TFTs. For a display device provided with such an image memory, it is requested to lower the driving voltage depending on the application of the display device.
In the above-described display device, since both of the p-type and n-type TFTs are provided, it is necessary to make lower the threshold voltages Vth of the p-type TFT and the n-type TFT, respectively, in order to further reduce the driving voltage.
However, the voltage-current characteristics (the Vg-Id characteristics) are different between the p-type TFT and the n-type TFT. Accordingly, it is difficult to adjust the threshold voltage Vth in such a manner that both of the TFTs are in the OFF state (normally OFF) when the gate voltage is zero (Vg=0 V). The reason will be described below in detail.
A semiconductor layer of a TFT is generally patterned so as to have a slope portion (a tapered portion) in the periphery. Accordingly, the threshold voltages Vth are different between the slope portion of the semiconductor layer and a flat portion with a flat surface. Specifically, as exemplarily shown in FIG. 46, in the TFTs of either type, i.e. in the n-type TFT and in the p-type TFT, the current-voltage curve in the slope portion is shifted (n-type conversion) to the side of the lower voltage than the current-voltage curve in the flat portion. The reason why the slope portion tends to be converted into n-type as compared with the flat portion is not known. From the experimental results executed by the inventors of the present invention, it is presumed that the slope portion of the semiconductor layer is damaged in the etching process or the asking process of the semiconductor layer (a silicon layer).
In FIG. 47, (a) and (b) are graphs exemplarily showing the voltage-current characteristics of the n-type TFT and the p-type TFT, respectively. The voltage-current characteristics of the respective TFTs are depicted by solid lines, and the current-voltage curves in the flat portion and the slope portion are depicted by dotted lines. As shown in the figure, the voltage-current characteristics of the respective TFT are curves obtained by overlaying the current-voltage curve of the flat portion and the current-voltage curve of the slope portion.
In the n-type TFT, as shown in FIG. 47(a), first, a drain current Id starts to flow at a lower voltage value Vg(e) in the slope portion. Then, at the voltage value Vg(m), the drain current Id starts to flow in the flat portion. The threshold voltage Vth is determined depending on the characteristics of the flat portion.
FIG. 48 is a plan view of the n-type TFT. As descried above, in the n-type TFT, first, the drain current Id(e) flows from a source region to a drain region in the slope portion positioned in the periphery of a semiconductor layer 1. Next, the drain current Id(e) starts to flow in the flat portion.
As described above, the drain current Id tends to rise in two stages (so-called occurrence of hump). That is, the slope portion functions as a parasitic transistor, which is actualized.
As shown in FIG. 49, in the n-type TFT, if a p-type impurity is doped (channel-doped) to the semiconductor layer, for example, the current-voltage curve can be shifted to the higher voltage side. Accordingly, it is possible to perform the adjustment in such a manner that the drain current Id has the minimum value (the OFF state) when the gate voltage Vg=0. However, if such adjustment is performed, the threshold voltage Vth is also shifted to the higher voltage side, so that the threshold voltage Vth cannot be lowered.
On the other hand, in the p-type TFT, as shown in FIG. 47(b), first, a drain current Id starts to flow in the flat portion at the voltage value Vg(m), and then flows in the slope portion at the voltage value Vg(e). The current flowing in the slope portion is extremely smaller than the current flowing in the flat portion. Accordingly, the characteristics of the parasitic transistor generated in the slope portion are hidden behind the characteristics of the flat portion, so as not to be actualized. Accordingly, in the p-type TFT, the threshold voltage Vth can be lowered when the gate voltage Vg is zero.
As described above, due to the characteristics of the parasitic transistor of the n-type TFT, it is difficult, when the gate voltage Vg is zero, to set both of the p-type TFT and the n-type TFT into the OFF state, and to lower the threshold voltage Vth.
In order to solve the problem, in Patent Document No. 1, it is suggested that the current-voltage curve of the parasitic transistor in the slope portion is shifted so as to be hidden behind the current-voltage curve in the flat portion by introducing the p-type impurity into the slope portion in the semiconductor layer of the n-type TFT with higher density than in the flat portion.
In FIG. 50, (a) and (b) are cross-sectional views for explaining the production method of the n-type TFT and the p-type TFT disclosed in Patent Document No. 1, respectively. Hereinafter, with reference to FIG. 50, the method disclosed in Patent Document No. 1 will be described.
First, a base insulating film 242 is formed on a substrate 241, and then a semiconductor film into which a p-type impurity (boron) is introduced is formed. Next, on the semiconductor film, a mask film of a silicon oxide film, for example, is formed.
Next, in a region in which an n-type TFT is to be formed and in a region in which a p-type TFT is to be formed on the substrate 241, resist films which cover a part of the mask film are formed, respectively.
Thereafter, by using the resist film as a mask, the semiconductor film and the mask film are etched in an island-like manner. As the result of the etching, an island-like semiconductor layer 243n and an island-like mask layer 244n are obtained in the region in which the n-type TFT is to be formed, and an island-like semiconductor layer 243p and an island-like mask layer 244p are obtained in the region in which the p-type TFT is to be formed. In the etching process, in the regions in which the respective TFTs are to be formed, edge portions of the resist films gradually move back. In accordance with this, portions of the semiconductor layer which are not covered with the resist films and the mask layers 244n and 244p are etched so as to be thinner as the distance from the edge portions of the mask layers 244n and 244p increases. Accordingly, in the periphery of the semiconductor layers 243n and 243p, slope portions are formed.
After the resist films are removed, as shown in (a) and (b) of FIG. 50, a resist film R4 is formed so as to cover the semiconductor layer 243p of the region in which the p-type TFT is to be formed and so as not to cover the semiconductor layer 243n of the region in which the n-type TFT is to be formed.
Next, a p-type impurity is introduced into the entire of the semiconductor layer 243n under the condition that the impurity is transmitted through the mask layer 244n. Then, the p-type impurity is selectively introduced into only a portion of the semiconductor layer 243n which is not covered with the mask layer 244n (a slope portion) under the condition that the impurity is not transmitted through the mask layer 244n. As a result, to the slope portion of the semiconductor layer 243n, the p-type impurity with volume density which is twice to five times as much as that of the flat portion is introduced. Accordingly, in the n-type TFT, it is possible to prevent the parasitic transistor in the slope portion of the semiconductor layer 243n from being actualized.
Thereafter, the resist film R4 is removed, and then, on the mask layers 244n and 244p, an insulating film and a gate electrode (not shown) are formed. The mask layer 244n and 244p and the insulating film are used as a gate insulating film.